1. Field of the Invention
This invention relates to improvements in semiconductor fabrication processes, and more particularly to improvements in semiconductor planarization processes, and to semiconductor products utilizing the improved planarization process of the invention.
2. Description of the Prior Art
In the fabrication of integrated circuits in many instances it is desired to provide a planarized surface, that is, a top surface for the integrated circuit that has relatively even or smooth topography. In typical manufacturing processes, a structure is made including patterned metal conductors formed on a stack of underlying structures and covered with a low temperature oxide, such as a plasma-enhanced oxide. The oxide is then covered with an insulating layer such as spin-on glass (SOG). The plasma-enhanced oxide is relatively conformal; consequently, it will have fairly significant hills overlying the regions of the stack of underlying structure on which metal has been deposited and patterned and steep valleys formed in-between. To planarize these hills and valleys, the spin-on glass is applied and etched back to attempt to achieve a smooth surface on the integrated circuit. However, as the spin-on glass is etched through in the regions overlying the metal, oxygen free radicals are released from the plasma-enhanced oxide which enhances the etch rate of the spin-on glass in the valley regions of the integrated circuit. The etch rate of the spin-on glass, for example, can be 50% or higher than that of the plasma-enhanced oxide, depending on the etch chemistry; thus, the planarization of the integrated circuit involves critical process parameters that are difficult to control, especially when an etch into the underlying plasma-enhanced oxide is required.